Testability design of most popular embedded module

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Design for testability including embedded modules

deep submicron technology makes the chip more and more complex, which means that many embedded modules cannot be tested by traditional methods. In order to ensure product quality, we must find new solutions

at the beginning of the new century, large and complex designs have become quite common. This paper analyzes the product quality problems of large-scale IC and ASIC design. At the same time, the testability design method with the ratio of height and diameter of 3:2 of some available low carbon steel compact specimens and the balance that may need to be made are also evaluated

challenges to the failure situation and failure mechanism of the analysis products of the design team

in the early 1990s, there were few large-scale designs. These designs usually take several years and a large-scale development team. Large scale design is generally structured design, such as mass-produced microprocessors. Product quality is guaranteed by the development of professional testing methods. These methods are often called structured design for testability (DFT) methods

dft allows the design team to modify the design in a predictable manner. Through simple modification, the production test can be created quickly enough, and the production test provides the necessary product quality

in the late 1990s, the adoption of logic synthesis and ASIC OEM led to an increase in DFT design requirements. However, it is estimated that only one third of all designs use DFT. Recently, many companies began to realize that they need to use scanning DFT

unfortunately, these companies realized the need for structured DFT only when design features began to affect testing methods. Design is no longer 100% logic. It regularly integrates logic, SRAM and dozens of embedded components. Million gate logic may represent only 50% of the silicon area. Obviously, all silicon must be tested to ensure product quality

different DFT methods must be understood in order to select the most effective solution. The solution must meet specific needs. The following section reviews the broad types of DFT methods and the methods used in testing embedded components

function test

the principle of function test is very simple. You can create a test based on the functional knowledge of the device. Well informed members of the design team can be responsible for developing test vector sets. The vector consists of two parts: the excitation factor of the device under test (DUT) and the corresponding expected response. This method requires professional design knowledge. Back in the past, the source of these vectors is the design simulation vector. They must meet the needs of the tester and usually need to be modified. It is worth noting that the simplest method from port output analog mode to test device requires periodic mode. This requires careful planning during simulation mode development, otherwise, these vectors may not be accepted by the test equipment

fault simulation software can be used to measure the test coverage of these modes. Years of experience has shown that this method is not easy to achieve high fault coverage. Improving fault coverage requires long-term analysis to establish additional modes. As you can see from Figure 2, this is the hardest part of vector creation

the time to develop these test vectors based on design functionality increases with the increase of design size and complexity. The interaction between design units (components) must be understood. This is a very simple task when the component is not embedded in the design. It is difficult for embedded components to create the same vector and provide the method of observing the expected results

fault simulation takes a lot of time, and the complexity increases in direct proportion to the square of the design size. There must be several large and powerful workstations. In order to reduce the amount of time required, fault simulation is usually decomposed into several machines. Many companies need more than a month to complete fault simulation

test access structure

because it is difficult to create function vectors for testing embedded components, it is very important to analyze how to apply DFT method. There are two basic methods available. In order to test embedded components without relying on surrounding design components, the direct access method can be used. This method is less automated than other methods, although some companies engaged in general core test reuse issues can provide some automation

traditional DFT methods or these evolved new methods can also be used. Usually these methods include scanning DFT or built-in self-test (BIST) methods

direct access

theoretically, the simplest way to test any embedded device in a design is direct access. This technique allows the reuse of tests and test vectors. As shown in Figure L, a path between the chip pin and the module port is provided for the port of each module. A unique test mode can be applied to every component or group of components to be tested

for unidirectional ports (input or output), a multiplexer structure can generally be used to provide a direct path. Bidirectional pins require special consideration. It must be ensured that there is no conflict between the drive direction of the component port and the chip pin. The vector of the multiplexing component also requires additional consideration for bidirectional signals

the test cost of an IC is proportional to its test time. If a design contains many embedded components, and each component is tested in turn, the test time will increase. As part of the design effort to provide direct access, consideration must be given to how to minimize testing time. It is necessary to determine which components can be tested in parallel. This requires the designer to analyze the design to determine components with similar test time

the complexity of the design increases faster than the number of chip signal pins. Usually, the number of ports of a specific type on a component exceeds the number of ports provided for the chip. The problem of pin type can be solved by changing the one-way chip pin to the two-way chip pin. If the number of ports on the component exceeds the number of chip pins, it must be possible to apply a subset of the test mode or use different DRT methods. It is worth noting that many design teams using intellectual property (IP) have begun to use this method

scanning DFT phase interface

in the late 1990s, scanning DFT method became more and more popular. It uses the method of producing predictable results to solve the complexity of the test sponsored by Taizhou Municipal People's government, Zhejiang Provincial Department of Commerce, China Plastics Processing Industry Association, China Plastics Machinery Industry Association and other units, and it is easy to operate automatically

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